1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which has a test mode.
2. Description of Related Art
JP2001-6396A describes a semiconductor integrated circuit which has a test mode for conducting a test for reading/writing data from/into memory cells.
In this semiconductor integrated circuit, serial data is applied not only in the test mode but also in a normal operation mode, and the serial data is converted to parallel data which is then output to a plurality of write units. Each write unit writes the data to a memory cell corresponding thereto in accordance with the data supplied thereto.
In the semiconductor integrated circuit described in JP2001-6396A, serial data is applied even in the normal operation mode, and the serial data is converted to parallel data which is simultaneously written into a plurality of memory cells.
For this reason, the semiconductor integrated circuit described in JP2001-6396A implies a problem that processing is required to convert serial data to parallel data in the normal operation mode.
FIG. 1 is a circuit diagram showing a semiconductor device which was designed by the inventors of the present application for solving the foregoing problem.
In FIG. 1, semiconductor device 100 comprises input unit 200, buffer unit 300, switch unit 400, and data write unit 500.
Input unit 200 includes four terminals DQ0-DQ3. Input unit 200 receives a write command (hereinafter called the “WRT command”) and a clock (hereinafter called “clk”) signal, and also receives data at terminals DQ0-DQ3.
In a normal operation mode, parallel data is applied to terminals DQ0-DQ3. In a test mode, on the other hand, serial data for testing is applied to terminal DQ0 among terminals DQ0-DQ3.
Buffer unit 300 includes DQ0 buffer circuit 3000, DQ1 buffer circuit 3001, DQ2 buffer circuit 3002, and DQ3 buffer circuit 3003.
DQ0 buffer circuit 3000, upon receipt of a WRT command and a clk signal from input unit 200, captures data received at terminal DQ0, and outputs the data as DataB0.
DQ1 buffer circuit 3001, upon receipt of a WRT command and a clk signal from input unit 200, captures data received at terminal DQ1, and outputs the data as DataB1.
DQ2 buffer circuit 3002, upon receipt of a WRT command and a clk signal from input unit 200, captures data received at terminal DQ2, and outputs the data as DataB2.
DQ3 buffer circuit 3003, upon receipt of a WRT command and a clk signal from input unit 200, captures data received at terminal DQ3, and outputs the data as DataB3.
Switch unit 400 includes switches SW1-SW3, and switch control unit 400A.
Switch control unit 400A connects switches SW1-SW3 to normal side terminals 4001-4003, respectively, when switch control unit 400A is not receiving control signal tes1dq which specifies the test mode, i.e., in the normal operation mode. On the other hand, switch control unit 400A connects switches SW1-SW3 to 1DQ test side terminals 400a-400c, respectively, when switch control unit 400A is receiving control signal tes1dq, i.e., in the test mode.
Specifically, normal side terminal 4001 is receiving DataB1, normal side terminal 4002 is receiving DataB2, and normal side terminal 4003 is receiving DataB3. Also, 1DQ test side terminals 400a-400c are receiving DataB0.
Data write unit 500 includes four write units SA0-SA3 and memory cell area 500a. Write units SA0-SA3 are mapped to terminals DQ0-DQ3, respectively. Specifically, write unit SA0 is mapped to terminal DQ0; write unit SA1 to terminal DQ1; and write unit SA2 to terminal DQ2; and write unit SA3 to terminal DQ3.
Each write unit SA0-SA3 comprises two bit lines, specifically, Bit line xT(x=0, 1, 2, 3) and Bit line xN (x=0, 1, 2, 3), where x corresponds to the suffix of SA.
Each bit line is arranged as shown in FIG. 1.
Each write unit SA0-SA3 writes information into memory cell area 500a based on data from switch unit 400.
Each write unit SA0-SA3 transmits a signal representative of data “1” to Bit line xT associated therewith when it receives data “1,” and transmits a signal representative of data “1” to Bit line xN associated therewith when it receives data “0” to write information into memory cell area 500a. 
Semiconductor device 100 receives parallel data at terminals DQ0-DQ3 in the normal operation mode, and reduces terminals DQ0-DQ3 into terminal DQ0 (particular terminal) in the test mode to receive serial test data for terminals DQ0-DQ3 at terminal DQ0.
Switch unit 400 outputs parallel data applied to terminals DQ0-DQ3 to write units SA0-SA3 corresponding to terminals DQ0-DQ3 in the normal operation mode. Each write unit SA0-SA3 writes data into a memory cell corresponding thereto in accordance with data applied thereto.
Also, switch unit 400 outputs DataB0 received at terminal DQ0 to each of write units SA0-SA3 in the test mode. Each write unit SA0-SA3 writes data into a memory cell corresponding thereto in accordance with DataB0 applied thereto.
In semiconductor device 100, parallel data is received at a plurality of terminals in the normal operation mode, so that semiconductor device 100 is free from the problem which is experienced by the semiconductor integrated circuit described in JP2001-6396.
Also, semiconductor device 100 reduces terminals DQ0-DQ3 into terminal DQ0 in the test mode.
Accordingly, when semiconductor device 100 is tested using a probe card in the test mode, the test can be conducted for terminals DQ0-DQ3 by connecting a probe arranged on the probe card to terminal DQ0 on semiconductor device 100. As such, movement of the probe card for changing the connection of the probe with terminal DQ can be reduced.
Reduced movements of the probe card provide the following advantages.
When the probe card is moved, friction occurs, as a matter of course, and fragments caused by the friction adversely affects a semiconductor device. When movement of the probe card is reduced, the adverse affection is reduced.
Also, when the probe card is moved, a positional relationship between the probe and the terminal can shift from a positional relationship between the probe and the terminal in design due to errors in mechanical positions. This can cause an increase in potential damages to the semiconductor device. When movement of the probe card is reduced, smaller damage to the semiconductor device will occur.
Further, in some tests, the proportion of the time period, in which the probe card is moved, to the time period, in which a semiconductor device is tested, may increase. With a reduction in movement of the probe card, less time is needed to move the probe card.
However, the inventor of the present application has recognized that semiconductor device 100 has a problem in that write units SA0-SA3, more specifically, a plurality of driving units corresponding to a plurality of terminals cannot be provided with a data pattern different from arbitrary parallel data (hereinafter also called the “data pattern”), for example, parallel data comprised of a plurality of data indicative of the same contents.
Specifically, as shown in FIG. 2, in semiconductor device 100, DataB0 applied to terminal DQ0 is output to each write unit SA0-SA3 in the test mode. Therefore, each write unit SA0-SA3 is provided only with parallel data comprised of a plurality of data indicative of the same contents. For this reason, in semiconductor device 100, an arbitrary data pattern cannot be provided to a plurality of write units SA0-SA3 in the test mode.
Consequently, a test is highly unlikely to be conducted in semiconductor device 100 in the test mode using, for example, a data pattern which can cause interference between write units, and the like.